10:54
Unknown
About Company
Intern-TechnicalThe selected intern candidate will be part of the IP verification/ VIP team in Solutions Group,
Synopsys , India and be based at Bangalore.
The focus area of activities would be Verification/ VIP/ Test Environment development in
System Verilog/ Vera in a VMM environment in one of the following domain
:USB3/USB2/Ethernet/MIPI
The intern will be taken through hands-on training in Verification methodologies such as VMM
and in the respective domain.
Subsequent to training, the nature of work would be on the following lines:
Understanding product architecture for VIP or Test environment, coding in one of the HVL such
as System Verilog, Verification of the blocks that are coded, understanding and implementing
functional coverage infrastructure. It will involve closely working as part of the product
development team.
Candidate Profile
The candidate must have completed Bachelors degree in electronics/ Electrical engg with
minimum 70% or 7.0 CGPA.
Partial or full completion of MS/MTech is preferable with overall grades of 7.0 or above.
Candidates with good problem solving skills and kknowledge of HDL such as Verilog with
strong concepts in OOPs and C++. Exposure to HVL Languages such as
SystemVerilog/Vera/SpecmanE is highly preferable. Aptitude to work in VLSI Verification domain is
a must and only those who are willing to put it extra effort and take up technical challenges need
apply .
CLICK HERE TO MORE DETAILS
apply here
Name: Synopsys
Website: www.synopsys.com
Job Details
Education: B.E/B.Tech/M.Tech
Experience: Freshers
Job Location: Bangalore
Job DescriptionIntern-TechnicalThe selected intern candidate will be part of the IP verification/ VIP team in Solutions Group,
Synopsys , India and be based at Bangalore.
The focus area of activities would be Verification/ VIP/ Test Environment development in
System Verilog/ Vera in a VMM environment in one of the following domain
:USB3/USB2/Ethernet/MIPI
The intern will be taken through hands-on training in Verification methodologies such as VMM
and in the respective domain.
Subsequent to training, the nature of work would be on the following lines:
Understanding product architecture for VIP or Test environment, coding in one of the HVL such
as System Verilog, Verification of the blocks that are coded, understanding and implementing
functional coverage infrastructure. It will involve closely working as part of the product
development team.
Candidate Profile
The candidate must have completed Bachelors degree in electronics/ Electrical engg with
minimum 70% or 7.0 CGPA.
Partial or full completion of MS/MTech is preferable with overall grades of 7.0 or above.
Candidates with good problem solving skills and kknowledge of HDL such as Verilog with
strong concepts in OOPs and C++. Exposure to HVL Languages such as
SystemVerilog/Vera/SpecmanE is highly preferable. Aptitude to work in VLSI Verification domain is
a must and only those who are willing to put it extra effort and take up technical challenges need
apply .
CLICK HERE TO MORE DETAILS
apply here
0 comments :
Post a Comment